----------------------------------------------------------------------------------
-- Company: 		 Johns Hopkins University
-- Engineer: 		 Kevin Green
-- 
-- Create Date:    00:31:47 11/30/2011 
-- Design Name:    lut_4
-- Module Name:    lut_4 - RTL 
-- Project Name:   top_gillis_green
-- Target Devices: 
-- Tool versions: 
-- Description:    This is the 4-bit look-up table.  Given a the black and white
--                 vector and player, an output vector with the possible valid
--                 moves is generated.
-- 
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity lut_4 is
    Port ( black : in  STD_LOGIC_VECTOR (7 downto 0);
           white : in  STD_LOGIC_VECTOR (7 downto 0);
           player : in  STD_LOGIC;
           data_out : out  STD_LOGIC_VECTOR (7 downto 0));
end lut_4;

architecture RTL of lut_4 is

begin

process(player, black, white) is
begin
		case player & black & white is
			when '0' & x"0102" => data_out <= x"04";
			when '0' & x"0106" => data_out <= x"08";
			when '0' & x"010a" => data_out <= x"04";
			when '1' & x"0201" => data_out <= x"04";
			when '0' & x"0204" => data_out <= x"08";
			when '1' & x"0204" => data_out <= x"01";
			when '0' & x"0205" => data_out <= x"08";
			when '1' & x"0209" => data_out <= x"04";
			when '1' & x"020c" => data_out <= x"01";
			when '0' & x"0304" => data_out <= x"08";
			when '0' & x"0402" => data_out <= x"01";
			when '1' & x"0402" => data_out <= x"08";
			when '1' & x"0403" => data_out <= x"08";
			when '1' & x"0408" => data_out <= x"02";
			when '1' & x"0409" => data_out <= x"02";
			when '0' & x"040a" => data_out <= x"01";
			when '1' & x"0502" => data_out <= x"08";
			when '1' & x"0508" => data_out <= x"02";
			when '1' & x"0601" => data_out <= x"08";
			when '1' & x"0608" => data_out <= x"01";
			when '0' & x"0804" => data_out <= x"02";
			when '0' & x"0805" => data_out <= x"02";
			when '0' & x"0806" => data_out <= x"01";
			when '0' & x"0902" => data_out <= x"04";
			when '0' & x"0904" => data_out <= x"02";
			when '1' & x"0a01" => data_out <= x"04";
			when '1' & x"0a04" => data_out <= x"01";
			when '0' & x"0c02" => data_out <= x"01";
			when others => data_out <= x"00";
		end case;
end process;


end RTL;

